A semiconductor device, such as, for example, a field effect transistor, is often formed with both back end of the line (BEOL) contacts to the gate and source/drain regions of the device to turn the device on/off and to allow current to flow through the device, respectively, and a middle of the line (MOL) contact to the body of the device between the source/drain regions to adjust threshold voltage (Vt).
Traditionally, conductive metals, such as tungsten (W) and aluminum (Al) have been deposited (e.g., by chemical vapor deposition (CVD), sputtering, etc.) into patterned openings (i.e., vias), which are present in the dielectric material of the metallization structure, to form both MOL and BEOL contacts. Recently, because of its lower electrical resistivity copper and copper alloys, which require plating, have become the preferred metal for filling the contact openings in both BEOL and MOL metallization structures.
Unfortunately, as circuit densities are increased, the aspect ratio (i.e., the ratio of height to width) for both BEOL and MOL contact (i.e., metallization) structures has increased and adequate plating of such high aspect ratio metallization structures has proven difficult. Specifically, as circuit densities increase and device sizes are scaled, the width of both BEOL and MOL contact (i.e., metallization) structures is decreased; however, the thickness of the dielectric layers in which these contacts are formed has remained the same (i.e., contact or metallization structures with high height to width ratios). For example, circuit designers currently require MOL and BEOL contacts with aspect ratios that are greater 6:1 and oftentimes greater than 10:1. When conventional plating techniques are used to fill these high aspect ratio openings, seams and voids (collectively referred to as a key-hole seam) develop within the contact (i.e., metallization) structure.
FIG. 1 is a prior art semiconductor structure 10 which includes a contact (i.e., metallization) structure 20. As shown, the prior art structure 10 includes a field effect transistor (FET) 12 including a material stack 14 comprising at least a gate dielectric and an overlying gate conductor; both are not specifically shown or labeled but are collectively meant to be included within material stack 14. The material stack 14, which is patterned, also has an upper surface 15 that comprises a metal semiconductor alloy, i.e., a metal silicide or metal germanide, contact. The FET is located on a surface of a semiconductor substrate (not specifically shown) in which the source/drain regions are present. The FET 12 includes at least one spacer 16 located on exposed sidewalls of the material stack 14. The contact structure 20 includes a dielectric material 22 having a high aspect contact opening that is filled with a conductive metal 24 such as W, Al or Cu which is in contact with the upper surface 15 (i.e., the metal semiconductor alloy) of the material stack 14. As is shown, and since prior plating processes have been used in forming the contact structure, a key-hole seam (represented by reference numeral 26) is present in the contact structure. The presence of the key-hole seam negatively affects contact performance and, as such, the formation of the same in a contact structure should be avoided.
In view of the above, there is a need for providing a new and improved high aspect ratio contact (hereinafter referred to as metallization) structure in which key-hole seam formation is avoided. That is, there is a need for providing a highly reliable high aspect ratio metallization structure in which key-hole seam formation within a high aspect ratio opening of the metallization structure is eliminated.